====== Acknowledgements ======

[[http://www.ncl.ac.uk/|{{:acknowledgement:logo-newcastle-w200.png?nolink|Newcastle University}}]]

Workcraft has been developed by several generations of PhD students and researchers at the [[http://www.ncl.ac.uk/eee/research/groups/micro/|μSystem Research Group]] (lead by Prof Alex Yakovlev) and [[http://www.ncl.ac.uk/computing/research/groups/amber/|AMBER Research Group]]:
  * Ivan Poliakov (Workcraft core, [[overview:graph|Directed Graph]], [[overview:petri|Petri Net]])
  * Arseniy Alekseyev (Workcraft core, [[overview:stg|Signal Transition Graph]])
  * Andrey Mokhov ([[overview:cpog|Conditional Partial Order Graph]], [[:scenco:start|SCENCO toolsuite]])
  * Stanislav Golubtsov (Workcraft core, [[overview:circuit|Digital Circuit]])
  * Danil Sokolov (Workcraft core, [[overview:dtd|Digital Timing Diagram]], [[overview:fsm|Finite State Machine]], [[overview:fst|Finite State Transducer]], [[overview:dfs|Dataflow Structure]], [[overview:policy|Policy Net]], [[overview:xmas|xMAS Circuit]], [[overview:wtg|Waveform Transition Graph]])
  * Bowen Li ([[overview:son|Structured Occurrence Net]])
  * Frank Burns ([[overview:xmas|xMAS Circuit]])
  * Victor Khomenko ([[:overview:backend_tools|back-end tools]] for verification and synthesis based on Petri net unfoldings)
  * Alessandro De Gennaro ([[overview:cpog|Conditional Partial Order Graph]], [[:scenco:start|SCENCO toolsuite]])
  * Jonathan Beaumont ([[overview:cpog|Conditional Partial Order Graph]], [[:plato:start|Plato toolsuite]])
  * Daniel Martí (build system, continuous integration, static code analysis)
  * Martin Jesper Low Madsen (OSX build)
  * Alberto Moreno ([[overview:wtg|Waveform Transition Graph]])
  * Alex Chan (eXtended Burst Mode)
  * Igor Wieczorek (Control Flow Logic translator)
  * Pete Austin, University of Liverpool (Parity Game solver)

[[http://www.epsrc.ac.uk/|{{:acknowledgement:logo-epsrc-w200.png?nolink|Engineering and Physical Sciences Research Council}}]]

[[http://www.epsrc.ac.uk/|EPSRC]] supported this activity by the following projects:
  * [[http://gow.epsrc.ac.uk/NGBOViewGrant.aspx?GrantRef=EP/D053064/1|SElf-timed DATapath synthEsis (SEDATE)]]
  * [[http://gow.epsrc.ac.uk/NGBOViewGrant.aspx?GrantRef=EP/I038551/1|Globally Asynchronous Elastic Logic Synthesis (GAELS)]]
  * [[http://homepages.cs.ncl.ac.uk/victor.khomenko/projects/pmc.html|A System for Parallel Model Checking]]
  * [[http://homepages.cs.ncl.ac.uk/victor.khomenko/projects/davac.html|Design And Verification of Asynchronous Circuits (DAVAC)]] (funded by The Royal Academy of Engineering and EPSRC)
  * [[http://homepages.cs.ncl.ac.uk/victor.khomenko/projects/verdad.html|VERification-Driven Asynchronous Design (VERDAD)]]
  * [[http://gow.epsrc.ac.uk/NGBOViewGrant.aspx?GrantRef=EP/K001698/1|UNderstanding COmplex system eVolution through structurEd behaviouRs (UNCOVER)]]
  * [[http://gow.epsrc.ac.uk/NGBOViewGrant.aspx?GrantRef=EP/L025507/1|Asynchronous design for Analogue electronics (A4A)]]
  * Dataflow Computation a la Carte

[[http://www.maxeler.com/|{{:acknowledgement:logo-maxeler-w200.png?nolink|Maxeler Technologies}}]]

The //Dataflow Computation a la Carte// project in collaboration with [[http://www.maxeler.com/|Maxeler Technologies]] and resulted in a plugin for modelling and analysis of dataflow structures with static and dynamic elements.

[[http://www.dialog-semiconductor.com/|{{:acknowledgement:logo-dialog-w200.png?nolink|Dialog Semiconductor}}]]

The recently started //Asynchronous design for Analogue electronics (A4A)// project is in collaboration with [[http://www.dialog-semiconductor.com/|Dialog Semiconductor]] and focuses on synthesis on CAD support for specification, synthesis and verification of asynchronous control logic for power management systems.