Circuit initialisation analyser (the last button in the Editor tools panel) to help identifying the gates that cannot be correctly initialised via the primary inputs and require explicit reset circuitry. A separate tutorial will be created to illustrate the usage of this tool.
Extra checks for circuit environment
STG. An
STG that has not been saved in a file cannot be set as a circuit environment – an error message is produced on such attempt. Also a warning is issued in case of a modified
STG being set as the circuit environment. Circuit conformation is denied without environment
STG.
Names of zero delay components are hidden by default. These names are usually irrelevant as they do not have associated signals for simulation or verification traces. Their visibility can be configured in Digital Circuit→Show names of zero delay components option of Edit→Preferences… menu.
Configurable suffixes for
STG signals (
signal_HIGH and
signal_LOW by default).
Force rendering of generalised C-elements as BOX.
Transformation tool for contraction of circuit joint.
Transformation tool for contraction of single-input circuit components.
Transformation tool for splitting wire joint points.
Transformation tool for toggling inversion of the gate pins.
Position new pins in the middle of BOX components, so the existing pin positions are preserved.
Improved GenLib parser that accepts keywords as module IDs (e.g. INV).
Circuit contact properties are filtered by IO type: Init to one, Forced init, Set function, Reset function are only visible on the driver pins (primary inputs and gate outputs).
Export unmapped gates into Verilog as assign statements (if set or reset functions are specified).