Configurable layout policy for editor tabs (scroll or wrap)

Adjusted dimensions of scroll buttons based on selected pixel density

Revise reset insertion procedure for excited gates

Conversion of circuits with constrained signals into STGs with disabled signal phases

Support for relative path in JavaScript setting of circuit environment models

Option to dissolve singleton bus on Verilog export

Option for set_disable_timing constraints in testable gates

Additional check on Verilog export that circuit components with the same label use the same refinement

JavaScript wrappers to access circuit contact methods

Global setting for visibility of set/reset functions on circuit contacts

Extend circuit statistics with the info on trivial gates (buf, inv, const)

Enable relocation of transition into existing arc by starting to drag it and pressing Ctrl

Implementation of a solver for parity game problem by Pete Austin, University of Liverpool