Add regex for user-defined auxiliary ports that should be excluded from output persistency check; the default is empty, and is configurable via Digital Circuit→Auxiliary ports regex to exclude from verification, e.g. sig|req[0-9]*|bus__\d+ of global preferences
Exclude scanout ports from output persistency check
Improve Output persistency property to accept exception pairs of signals for WAIT elements
Improve reporting of structural issues on Verilog import, e.g. for inconsistently connected nets and multiple top level modules
Extend substitution rules to enable user-defined extra gate pins, e.g. for scan
Add info on invalid files into refinement statistics that is accessible via Tools→Statistics→Refinement analysis
Use colors defined in Signals settings of global preferences when rendering contact names
Improve snapping to grid when creating nets with Connect tool