Add possibility to accept inout ports on Verilog import and filter out their connections (useful for ignoring VDD/GND inout ports)

Improve Verilog parser to handle complex delay expressions in assign statements

Convert assignments with xor and equivalence operators into not/and/or basis on Verilog export (for consistency with parser for Verilog import)

Optimise away double negations in assign statements on Verilog export

Recognise C-elements with input bubbles when using standard C synthesis mode

New exporter of mapped gates as Verilog assign statements

Uniform pin positioning for simple gates

Reload gate library if its GenLib file is modified

Fix colouring of signal events when simulating violation trace

Restrict the number of reported encoding conflicts for clarity and improve visualisation details when a single encoding conflict is selected

Improved verification of input properness with user-defined exceptions

Extend verification of delay insensitive interface by forbidding pulses on input signals

Support read arcs in verification of delay insensitive interface

Improve local self-triggering check by reducing the number of potential exceptions in to syntactic self-triggers

Promote delay insensitive interface and absence of local self-triggering to essential verification properties

Improve reports for N-way conformation by taking into account those continuations of violation traces that lead to internal signals

While holding Alt/AltGr, highlight master place for selected proxy and all proxies for selected master place

Warn about large graph before layout of ProFlo generated STG

Bugfix for creating groups/pages with proxy places whose master places belong to different groups/pages

Bugfix for import of .g file with place names clashing with internal connection names

Bugfix for long file path when Reach property with user-defined exception is encoded into the file name