Refinement models as a property of circuit components and STGs

Navigation through refinement models via popup menu or double-clicking

Export of a circuit with refined components into a hierarchical Verilog netlist

Import of hierarchical Verilog netlist as a circuit with refinement models for its components (the user can select the top module)

Improved support for “substitution rules” on import/export of Verilog netlists. Now separate conversion files can be specified for import and export, with possibility to invert the rules (e.g. when the same conversion file is used both for import an export)

Add an extra row in the violation report for N-way conformation (Table and List styles) that characterises the problematic output.

Handling the violation of place promised capacity during simulation. A warning dialog box appears once for each place whose promised capacity is violated.

Convert Petri net to multiple synchronised FSMs (Convert→Synchronised FSMs [MSFSM])

Convert STG to multiple synchronised FSTs (Convert→Synchronised FSTs [MSFSM])

Settings for configuration of MSFSM backend (Edit→Preferences…→External tools→MSFSM)

Note that MSFSM backend is still under development and is bundled with Workcraft yet. Its Linux binaries and conversion examples are available in this repo: https://github.com/workcraft/msfsm. To activate the tool put the msfsm_tools binary in tools/MSFSM directory and enable it via Activate MSFSM backend (experimental) – requires restart setting.