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| tutorial:synthesis:start [2015/02/12 21:30] – danil | tutorial:synthesis:start [2020/04/01 17:08] (current) – removed danil |
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| ====== Synthesis and verification of asynchronous circuits ====== | |
| <WRAP important> | |
| Familiarise yourself with the [[:help:stg_plugin|Signal Transition Graph plugin]] and [[:help:digital_circuit_plugin|Digital Circuit plugin]] before proceeding with these tutorials. | |
| </WRAP> | |
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| A Signal Transition Graph (STG) is basically a [[wp>Petri net]] whose transitions are labelled with signal events. This makes STG a convenient formalism for specification, synthesis and verification of [[wp>asynchronous circuit|asynchronous circuits]]. In this series of tutorials you will learn how to specify the intended behaviour of an asynchronous circuit using [[:overview:stg|Signal Transition Graphs]] plugin, synthesise its asynchronous implementation, capture the circuit schematic in [[:overview:digital_circuit|Digital Circuit]] plugin and formally verify it against the initial specification. | |
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| * [[:tutorial:synthesis:celement:start|Synthesis and verification of C-element]] (basic circuit, detail explanation) | |
| * [[:tutorial:synthesis:buck:start|Synthesis and verification of buck control]] (medium complexity with some hints) | |
| * [[:tutorial:synthesis:vme:start|Synthesis and verification of VME bus controller]] (advanced material for individual work) | |
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